RTL Engineer- CPU Load/Store Unit (LSU)
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. CPU Microarchitecture/RTL engineer focusing on high-performance CPUs. The person coming into this role will work with a highly experienced team and deliver a functional, performant, timing and power converged block.This role is Hybrid, based out of Austin, TX or Santa Clara, CA. Responsibilities:RTL design and Microarchitecture of the Load/Store unit for a from-scratch high performance CPU based on RISC-V ISA, working closely with the DV and PD teamRTL coding in Verilog leveraging on both industry tools as well as open-source infrastructureWork with design, test and post silicon validation teams for high quality deliveryDrive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goalsDeploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power resultsDebug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environmentEnhance RTL design environment, tools and infrastructure Experience & Qualifications:BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experienceStrong background and experience with high performance OOO CPU microarchitectureExperience working on an x86, ARM or RISC-V based CPUArchitectural understanding of the load/store engines, memory consistency, MMU, Interface protocols for an Out of Order CPUExpertise in logic design and ability to evaluate functional, performance, timing and power for you designStrong experience with hardware description languages (Verilog, VHDL), simulators (VCS, NC, Verilator), Synthesis and Power toolsExpertise in microarchitecture definition and specification developmentStrong problem solving and debug skills across various levels of design hierarchies Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.
Location: Austin, Texas, United States; Santa Clara, California, United States
Salary range: None - None