Tenstorrent's Posts (144)

CPU Core Unit Lead

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. CPU Core Unit Lead will play a key role in developing next-generation CPU RTL. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification. This role is Remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - CPU Core Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (vector execution, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure. - CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA. - AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process - Mentoring Junior Engineers: mentor team members as the lead. - Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - Proven track record of designing high-performance CPU RTL. - Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…) - Deep understanding of CPU microarchitecture and PPA trade-off. - Basic understanding of RISC-V Architecture including V-extension is preferred - Proficiency in hardware description languages (HDLs) such as Verilog or VHDL. - Excellent problem-solving abilities and analytical skills. - Strong communication skills, with the ability to convey complex technical concepts to diverse audiences. - Ability to work collaboratively in a team-oriented environment and across multiple disciplines.

Location: United States

Salary range: None - None

CPU Architect, Load-Store

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on the CPU’s load-store unit. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures with an emphasis on a high-performance load-store unit. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design. This role isRemote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Drive the architecture, micro-architecture, design and optimization of the CPU load-store unit for Tenstorrent’s high-performance out-of-order RISCV CPUs - Propose new implementations to optimize load-store PPA - Perform simulations, modeling, and performance analysis of advanced CPU features and state-of-the-art data prefetchers - Collaborate with hardware and software teams to optimize memory access patterns and system performance. - Stay up to date with industry trends and emerging technologies in CPU architecture and the memory subsystem - Support documentation and presentation of architectural decisions, trade-offs, and findings. - Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience). - Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and data prefetching - Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar). - Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++). - Problem-solving skills and ability to analyze complex system interactions. - Excellent communication and teamwork abilities. - Hands-on experience with performance profiling tools and benchmarking methodologies. - Exposure to parallel processing architectures and multi-core systems.

Location: United States

Salary range: None - None

CPU Architect, Memory Subsystem & Interconnects

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a highly motivated and passionate CPU Architect to join our processor architecture team, focusing on memory subsystem and interconnects. In this role, you will contribute to the design, analysis, and optimization of cutting-edge CPU architectures. This is an excellent opportunity to work alongside world class architects in high-performance computing and processor design. This role ishybrid, based out of Santa Clara, CA, Austin, TX, Boston, MA, or Remote in the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Assist in the design and optimization of memory subsystems, including cache hierarchies, coherence protocols, and memory controllers. - Contribute to the development of high-performance interconnect architectures, including on-chip networks and chip-to-chip interfaces. - Perform simulations, modeling, and performance analysis of memory and interconnect components. - Collaborate with hardware and software teams to optimize memory access patterns and system performance. - Stay up to date with industry trends and emerging technologies in CPU architecture, memory, and interconnects. - Support documentation and presentation of architectural decisions, trade-offs, and findings. - Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science (or equivalent experience). - Strong understanding of computer architecture fundamentals, including memory hierarchy, cache coherence, and interconnect topologies. - Familiarity with performance modeling and simulation tools (e.g., Gem5, SimpleScalar, or similar). - Basic knowledge of hardware description languages (e.g., Verilog, VHDL) and system-level programming (C, C++). - Problem-solving skills and ability to analyze complex system interactions. - Excellent communication and teamwork abilities. - Hands-on experience with performance profiling tools and benchmarking methodologies. - Exposure to parallel processing architectures and multi-core systems. - Knowledge of DDR, HBM, and other emerging memory technologies. - Experience with interconnect protocols such as AXI, PCIe, or CXL.

Location: United States

Salary range: None - None

Data and DevOps Engineer, Architecture

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent designs and optimizes high-performance computer systems using open standards and open-source software. Our Platform Architecture team leverages simulations, data analysis, and data-driven decision-making to prioritize features for our product roadmap. We’re seeking a hands-on problem solver to manage data pipelines associated with performance metrics, to help monitor the Slurm cluster where simulations run to generate those metrics, and to improve workflows that support hardware architecture refinement. You'll work closely with experts across multiple disciplines to enable data-driven insights for optimizing future-generation CPUs and AI systems. Join us to enable smarter workflows and optimize innovative hardware products shaping the future of computing. This role isremote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Design dashboards and automate performance tracking for software workloads on simulations of multiple generations of future RISC-V CPUs and heterogeneous chiplet-based systems. - Maintain or migrate custom data analysis workflows to scalable platforms like relational databases and Apache Superset. - Efficiently manage, store, and enable the team to utilize large datasets. - Take ownership of shared tools and workflows by engaging continuously with architecture and design projects as they move through the product development lifecycle. - Collaborate with engineers and architects who are seeking to evaluate performance tradeoffs in our product design by obtaining data-driven insight. - Streamline resource allocation and scheduling for CI/regression tests running on a Slurm cluster, ensuring optimal utilization of compute, storage, and network resources. - Identify resource needs and participate in purchasing decisions or introducing new software tools to our analysis workflows. - Implement improvements to our methodologies to define and launch simulation experiments and tests. - Develop solutions to detect, categorize, and report workflow and job failures in Slurm, CI systems, and data pipelines - Master’s degree in data engineering or another similar field. - 5+ years of experience in developing data pipelines and automation. - Proven track record of creating dashboards or interactive data visualizations, with preference for making it easy to share, extend, or modify the visualization for further analysis by using Apache Superset or similar Business Intelligence tools. - Proficiency in Python. - Experience using and configuring Linux systems. - Experience writing SQL queries (e.g., to query Postgres or SQLite). - Basic familiarity with git version control. - Some experience building C/C++ tools from source. - Experience with automated pipelines that integrate with local or cloud-based services (e.g., with REST APIs), such as CI/CD or test automation systems. - Experience in Linux cluster administration or working with batch schedulers (e.g., Slurm). - Experience running and gathering data from any simulation or modeling tool. - Knowledge of computer hardware design or CPU performance benchmarks (e.g., SPEC INT, Geekbench).

Location: United States

Salary range: None - None

CPU Core Design Verification Engineer - Contractor

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for CPU core level feature / testplan verification contractors responsible for ISA and microarchitectural verification. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We are open to the idea of remote on a case by case basis. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Functional verification with emphasis on core level testplanning, stimulus development and regression debug for simulation and emulation regressions - Understand ISA and microarchitectural specifications for the Core and create comprehensive testplans - Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments - Develop architectural and microarchitectural coverage for core features and create stimulus for closing coverage in a timely manner - Support design deployment across simulation and emulation platforms - Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain - Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster - BS/MS/PhD in EE/ECE/CE/CSwith at least 5 years of experience - Strong background and experience with high performance OOO CPU microarchitecture - Experience and understanding of one or more ISAs - x86, ARM or RISCV - Experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug - Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios - Familiar with simulation, formal and emulation environments - Hands-on with scripting (Python, PERL) - Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator) - Strong problem solving and debug skills across various levels of design hierarchies

Location: United States

Salary range: None - None

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