Tenstorrent's Posts (144)

2025-07-19

Sr. Staff, Digital Design Verification Engineer, Chiplets

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for an experienced Digital DV Engineer to join our team. At Tenstorrent you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated team. We are looking for a DV Engineer to develop verification methodology for our products. This role isremote, based out of Taiwan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Verification of Tenstorrent's digital IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, emulation - Creation of test plans - Writing testbenches, checkers and tests, models, assertions and irritators - Creating functional coverage points - Reviewing verification results and metrics and, driving the verification convergence towards tape-out - Performance and power verification and validation of Tenstorrent's IP and SOC - At least 8 years of experience in hardware verification languages (SystemVerilog, SystemC) - Bachelor/Master in Electrical/Computer Engineering/Engineering Science - Experience with UVM and coverage driven constrained random verification - Experience with Low power verification techniques - Excellent programming skills. C/C++ as well as scripting languages (Perl, tcl) - Deep interest in computer architecture

Location: 泰安, New Taipei City, Taiwan

Salary range: None - None

2025-07-19

Sr. Staff, Physical Design Engineer - Chiplets

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're building fast silicon and integrating it into a chiplet-based system — and we need people who can help close that loop. This isn’t just a PnR role — it’s about owning the last mile between great architecture and real silicon. If you know physical design or want to level up fast in it, and care about making hard things work, we’ve got room at the table. This role is hybrid based out of Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are What We Need What You Will Learn Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Deeply curious about how high-performance silicon gets built and delivered. - Comfortable in the weeds — timing reports, power grids, clock trees, layout blocks. - Interested in how chiplets change physical design, integration, and packaging. - A builder who sees constraints as part of the fun, not a reason to back off. - An engineer to help bring high-speed CPU cores from RTL to physical silicon. - Someone comfortable working across synthesis, place & route, timing, and signoff to ensure clean chiplet integration. - A strong collaborator who can align physical implementation with architectural and verification intent. - A practical problem-solver who improves slow parts of the flow, automates what’s repetitive, and catches issues early. - How chiplet architecture reshapes the rules of physical design and timing. - What it takes to build a system where the silicon, packaging, and performance all align. - Why real closure isn’t about tools — it’s about understanding the system. - How a tightly integrated team moves fast across disciplines and tapeouts.

Location: United States

Salary range: None - None

2025-07-19

Staff, Software Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will develop software for our RISC-V CPU chiplet. This role ison-site, based out of Tokyo, Japan. Responsibilities: Experience & Qualifications: Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Design, develop, and optimize system software for RISC-V-based systems. - Collaborate with cross-functional teams to define software requirements and specifications. - Participate in development and maintenance of software stacks, including Operating Systems, drivers, firmware, and libraries, to support our hardware platforms. - Implement and optimize system software, and contribute to workload optimization. - Troubleshoot and resolve software and system-level issues. - Develop and maintain software development processes, tools, and methodologies to ensure high-quality code and timely delivery. - Stay up-to-date and engaged with the latest industry trends and advancements in RISC-V, AI, and ML technologies. - Regular communication/travel to Australia and USA to meet with the team. - Fluent in English - Bachelor's degree or higher in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent work experience. - Strong debugging, problem-solving, and analytical skills. - Excellent communication and teamwork abilities. - Proven experience in delivering complex system software products to customers and internal stakeholders. - 5+ years of professional experience in system software engineering. - Solid understanding of RISC-V architecture and instruction set. - Experience with Linux kernel development and device driver programming. - Experience with product development of embedded software and real-time solutions is a plus. - Strong coding skills in C/C++/ASM and one or more of Python, Rust or Go.

Location: Japan

Salary range: None - None

2025-07-19

STA Lead, Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for STA timing analysis using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus. This role isRemote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Full chip timing analysis from early investigation to final implementation and tape out. - Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure. - Work with architects and logic designers to generate block and full chip timing constraints. - Analyze scenarios and margin strategies with Synthesis & Design team. - Partner with physical design teams to close and sign off the designs through PnR and ECO cycles. - PhD, Masters or Bachelors Degree in EE, EECS or CS. - Hands-on experience in ASIC timing constraints generation and timing closure. - Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC etc.). - Deep understanding and experience in timing closure of various functional and test modes - Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, POCV, IR-STA). - Proficient in scripting (TCL, Perl, Python, csh/bash). - Problem solver, Efficient written and verbal communication, Excellent organization skills and Mentorship quality. - Self starter and highly motivated. - Ability to work cross-functionally with various teams and be productive under aggressive schedules.

Location: United States

Salary range: None - None

2025-07-19

Senior Physical Design Engineer - CTS

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. CTS Methodology Lead for high-performance designs going into industry leading CPU and AI/ML architecture. This role involves owning and driving CTS methodology development and implementation, and help define and refine clock architecture strategies (e.g., traditional CTS, H-tree, mesh) for a variety of high-performance designs. This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Own and drive CTS methodology development and implementation, ensuring industry-leading clock quality and performance. - Define and refine clock architecture strategies (e.g., traditional CTS, H-tree, mesh) for a variety of high-performance designs. - Utilize physical design tools (PNR) to design, implement, and optimize complex clock trees. - Optimize clock non-default rules (NDRs) to achieve minimal insertion delays, skew, and maximize overall power, performance, and area (PPA). - Remain hands-on with timing closure processes and collaborate with RTL, DFT, and physical implementation teams to resolve clocking challenges. - Evaluate and benchmark new CTS flows and tools; contribute to tool evaluations and methodology improvements. - Document methodologies and best practices; provide guidance and training to design teams. - Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks, and design closure. - BS/MS/PhD in Electrical Engineering, Electronics, Computer Engineering, or Computer Science. - 5–10 years of relevant industry experience in physical design and CTS implementation. - Prior experience executing designs at leading edge technology nodes - Proven experience owning and delivering CTS for complex, high-performance ASIC or SoC designs. - Proficient in using place-and-route (PNR) tools for clock implementation and optimization. - Strong understanding of clocking methodologies, including mesh, H-tree, and traditional CTS strategies. - In-depth expertise in optimizing clock non-default rules (NDRs) for minimal insertion delay, skew, and improved PPA. - Familiarity with DFT clocking concepts is highly desirable. - Hands-on experience with synthesis and place and route using industry standard tools - Strong programming/scripting skills in Tcl, Perl, Shell, and Python. - Excellent verbal and written communication skills; collaborative attitude. - Ability to thrive in a fast-paced, innovative environment.

Location: Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States

Salary range: None - None

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