Tenstorrent's Posts (144)

Sr. Engineer, Design Verification - AI Hardware

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix Team is transforming AI computing by building next-generation AI accelerators that challenge industry norms. As a Design Verification engineer, you’ll help make that vision a reality by validating advanced Tensix cores, RISC-V processors, and chiplet architectures powering everything from data center inference to edge AI. By contributing to our open-source ecosystem, you'll help ensure our hardware delivers the performance and reliability needed to redefine AI acceleration. This role is hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are What We Need What You Will Learn Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Skilled in modern DV methodologies, with experience building scalable, reusable verification environments for complex designs. - Passionate about AI hardware and familiar with neural network operations, floating-point arithmetic, and the challenges of verifying AI accelerators.Comfortable with a range of verification techniques, including constrained random testing, assertions, coverage analysis, and formal methods.A team player who collaborates closely with architecture, design, and software groups to validate innovative processor designs. - A verification engineer who enjoys finding edge cases and breaking things creatively. - Deep experience verifying complex IP, SoCs, and multi-core systems, including emulation platforms and workload acceleration. - Strong debugging skills and a track record of closing coverage gaps at block and full-chip levels. - Familiarity with memory systems and interconnect protocols, with bonus points for AI/ML accelerator or RISC-V experience. - How to verify advanced AI architectures that integrate RISC-V CPUs with specialized Tensix cores. - Techniques for building and optimizing environments for chiplet-based designs and scalable interconnects. - Hands-on experience with open-source verification flows while contributing to Tenstorrent’s software stacks. - How to shape the future of AI hardware verification while working with top engineers on breakthrough technology.

Location: Belgrade, Belgrade, Serbia

Salary range: None - None

Design Verification Engineer, AI HW - Contractor

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced Senior-Level Design Verification Engineer (Contract) to join our dynamic and innovative team. As a AI HW Design Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs through comprehensive verification methodologies. The successful candidate will have a strong background in verification techniques, excellent problem-solving skills, and a passion for delivering high-quality designs. This job is hybrid, based out of Austin, TX; Santa Clara, CA; Boston, MA; or Toronto, ON. Experience & Qualifications: Preferred Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Develop and execute comprehensive verification strategies to validate complex digital designs, ensuring compliance with specifications and standards. - Collaborate closely with design teams to understand design requirements and contribute to the creation of verification plans and testbenches. - Write and execute test cases to verify functionality, performance, and power aspects of the design. - Perform functional and formal verification to identify and debug design issues and ensure correct design behavior. - Develop and maintain verification infrastructure, methodologies, and best practices to improve efficiency and productivity. - Drive the adoption of advanced verification methodologies, tools, and techniques to enhance the overall verification process. - Mentor and provide technical guidance to junior verification engineers, sharing expertise and best practices. - Collaborate with cross-functional teams to analyze and resolve system-level issues and ensure seamless integration of the design. - Stay updated with the latest industry trends, emerging technologies, and verification methodologies to drive innovation and continuous improvement. - Bachelor's or Master's degree in Electrical/Computer Engineering or a related field. - Proven experience as a Design Verification Engineer, with a focus on complex digital designs. - Strong knowledge of digital design concepts, including RTL, synthesis, and timing constraints. - Proficiency in verification methodologies such as UVM (Universal Verification Methodology) and SystemVerilog. - Experience in developing and executing verification plans, testbenches, and test cases for digital designs. - Solid understanding of functional coverage, assertion-based verification, and code coverage analysis. - Proficiency in scripting and programming languages like Python, Perl, or C/C++. - Familiarity with industry-standard EDA tools and simulation environments. - Excellent problem-solving and debugging skills, with a keen eye for detail. - Strong communication and interpersonal skills, with the ability to collaborate effectively in a team-oriented environment. - Proven ability to work under tight deadlines and deliver high-quality results. - Python/CocoTB/PyUVM experience is a big plus. - Experience with emulators

Location: United States

Salary range: None - None

Chiplet Emulation Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will help build emulation infrastructure for a System-in-package for high-performance AI/ML engines. This role requires a strong technical background and a problem-solver mindset. This role ishybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Nice to Have: Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Help build a state-of-the-art hardware emulation ecosystem including,Build flow for emulation models with optimum frequency and emulation footprintWrite emulation test-benches for single and multi chiplet models and transactors, monitors and harness componentsWrite test plans focusing on unique functional coverage, performance, power extraction and low level software developmentExecute test plans, summarize the results and share feedback with project stakeholders - Build flow for emulation models with optimum frequency and emulation footprint - Write emulation test-benches for single and multi chiplet models and transactors, monitors and harness components - Write test plans focusing on unique functional coverage, performance, power extraction and low level software development - Execute test plans, summarize the results and share feedback with project stakeholders - Develop synthetic components for custom transactors, monitors, checkers, etc… - Work across boundaries with architects, software and design/verification teams to define and improve the emulation platform - Build flow for emulation models with optimum frequency and emulation footprint - Write emulation test-benches for single and multi chiplet models and transactors, monitors and harness components - Write test plans focusing on unique functional coverage, performance, power extraction and low level software development - Execute test plans, summarize the results and share feedback with project stakeholders - Advanced degree in electrical engineering, computer engineering, or computer science - Proven experience in emulation/design, with a strong track record of successful projects - Proficiency with Synopsys Zebu and/or Cadence Palladium, with the ability to adapt to various emulation platforms as needed - Understanding of logic design and mapping design to emulation hardware - Knowledge in Verilog/system Verilog - Knowledge of emulation tools, flows, scripting and automation - Good problem solving skills, organizational and communication skills - Good English language skills (written and spoken) - Experience with Cadence Palladium - Knowledge of C, C++ or SystemC - Knowledge of RISC-V, CPU microarchitecture, machine learning, die-to-die, memory controllers, PCIe, UCIe - Understanding of verification - Fluency in Japanese - Japanese work visa

Location: Japan

Salary range: None - None

Chiplet Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for synthesis and place and route using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus. This role isbased out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Synthesis and Place and Route using industry standard tools for high speed CPU core design - Plan out resources, schedule, project PPA - Develop strategies to deliver reproducible design convergence results - Help to create and refine synthesis and PNR flow for the project team - Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure - Develop and recommend better design methodologies to enable better timing convergence - Plan out resources, schedule, project PPA - Guide and mentor junior engineers - PV convergence (including static timing and power analysis) - Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks - Scripting in an interpreted language, minimum TCL in addition to at least one other - Advanced degree in electrical, computer engineering or computer science - Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure - Experience with PV convergence, including static timing and power analysis - Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks - Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools - Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs - Expertise in timing closure and block/chip levels and ECO flows - Experience with scripting in an interpreted language (Python, TCL) - Willingness to work with others in a highly complex decision space - Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule - Excellent verbal and written communication in English, and collaboration skills - Fluency in Japanese. - Japanese work visa.

Location: Japan

Salary range: None - None

CPU Workload Performance Optimization Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a CPU Workload Performance Optimization Engineer to drive the characterization, analysis, and optimization of CPU workloads for Tenstorrent’s cutting-edge processor products. In this role, you will work closely with architects, hardware designers, and software engineers to analyze CPU applications, enhance compilers and runtimes, and drive workload performance optimizations. Your contributions will directly shape the design and implementation of next-generation high-performance computing platforms across a diverse set of workloads. This role is open to Santa Clara, CA, Austin, TX, Boston, MA, Toronto, ON, Ottawa, ON, or open to Remote in North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Conduct competitive analysis to evaluate the strengths and weaknesses of compilers and runtimes for key workloads - Analyze binary disassemblies and instruction traces to identify inefficiencies in RISC-V compiler and/or runtime optimizations. - Propose and prototype new performance optimization features in RISC-V compilers and/or runtimes. - Optimize key workload performance by fine-tuning compiler flags and runtime configurations. - Develop handwritten kernels using intrinsic programming or assembly to enhance performance on existing hardware. - Build and enhance open-source tools to automate binary code quality checks or instrument binaries for performance analysis. - Publish performance tuning guidelines and best practices for internal teams, external developers, and customers. - Stay up to date with industry trends, emerging workloads, and advancements in compiler optimization techniques. - Ph.D. in Computer Engineering, Electrical Engineering, or a related field. - Strong research background in static or dynamic compilation techniques, focusing on middle-end and/or backend optimization. - Deep expertise in GCC, LLVM, or JIT compiler design, development, and optimization. - Extensive experience in workload performance bottleneck troubleshooting and mitigation. - Solid background in handwritten kernel development using intrinsic or assembly programming. - Strong understanding of CPU microarchitecture, including superscalar pipelines, speculative execution, SIMD, and memory hierarchy. - In-depth knowledge of operating system internals and GNU libraries. - Proficiency in C/C++, intrinsic/assembly programming, and scripting languages such as Python and Shell. - Excellent problem-solving and communication skills, with the ability to work across multidisciplinary teams. - Experience with compute library kernel development. - Knowledge of vector-length agnostic programming. - Experience with binary instrumentation or binary translation. - Expertise in memory management and data layout optimization.

Location: United States

Salary range: None - None

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