Tenstorrent's Posts (144)

2025-06-17

Automotive RTL Designer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced RTL Design Engineer for our fast-growing automotive SoC developments. In this role you will work on various aspects of the Tenstorrent Automotive chiplets. You will work closely with cross-functional teams, including verification engineers, software developers, and system architects, to ensure successful development of the automotive chiplet SoC. This role isRemote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Work closely with architecture, verification and the rest of the team to ensure a successful product - Work on IP integration of key subsystems. - Develop key automotive modules and write detailed microarchitecture specifications. - Work with internal and external stakeholders on chiplet level integration. - Evaluate and configure IP for key components - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - Strong knowledge of SystemVerilog and RTL design. - Experience developing complex RTL modules. - Experience in IP integration. - NoC, DDR, CPU or IO IP configuration experience. - ISP / GPU / ML accelerator experience is a strong plus. - Solid understanding of computer architecture, interconnects and memory system behaviour - Experience with functional safety / ISO26262 is a strong plus. - Experience with AEC-Q100/104 and automotive device reliability is a plus. - Strong problem-solving skills and the ability to analyse complex system-level issues. - Excellent communication skills

Location: United States

Salary range: None - None

2025-06-17

CAD & Methodology Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. As part of the Hardware Technology CAD team, you’ll help design our next-generation, high-performance, power-efficient SoCs. You will work on world class CPU, GPU, Analog/Mixed Signal and SOC designs by developing flows, tools and methodologies for future Tenstorrent products! You will explore and enable new technology nodes, stdcells and tools for design teams. You will collaborate with design teams and tool vendors to improve PPA (Power, Performance, Area) and design productivity. You will actively work on developing internal methodologies using your understanding of CAD algorithms and ML. We are looking for passionate engineers to join our team. This role isRemote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Participating and engaging with cross functional teams to tackle key physical design challenges. - Developing innovative solutions in physical design and optimization space. - Developing and supporting implementation flows for multiple projects and design teams. - Developing and maintaining custom CAD tools for implementation and signoff. - Creating flows to enable successful deployment of new technology nodes. - Developing tools and methodologies for best-in-class PPA and productivity including ML based solutions. - Collaborating with other teams such as physical design verification, RC extraction, IR and static timing analysis (STA). - Working directly with EDA tool vendors to resolve tool issues and identify areas for tool improvements. - Scripting in an interpreted language, minimum TCL in addition to at least one other - Bachelor, Master or PhD degree in electrical, computer engineering or computer science. - At least 5 years of relevant industry experience. - Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. - Experience with PV convergence, including static timing and power analysis. - Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks. - Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools. - Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs. - Expertise in timing closure and block/chip levels and ECO flows. - Experience with scripting in an interpreted language (Python, TCL). - Willingness to work with others in a highly complex decision space. - Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule. - Excellent verbal and written communication in English, and collaboration skills.

Location: United States

Salary range: None - None

2025-06-17

Chiplet Emulation Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will help build emulation infrastructure for a System-in-package for high-performance AI/ML engines. This role requires a strong technical background and a problem-solver mindset. This role ishybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Nice to Have: Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Help build a state-of-the-art hardware emulation ecosystem including,Build flow for emulation models with optimum frequency and emulation footprintWrite emulation test-benches for single and multi chiplet models and transactors, monitors and harness componentsWrite test plans focusing on unique functional coverage, performance, power extraction and low level software developmentExecute test plans, summarize the results and share feedback with project stakeholders - Build flow for emulation models with optimum frequency and emulation footprint - Write emulation test-benches for single and multi chiplet models and transactors, monitors and harness components - Write test plans focusing on unique functional coverage, performance, power extraction and low level software development - Execute test plans, summarize the results and share feedback with project stakeholders - Develop synthetic components for custom transactors, monitors, checkers, etc… - Work across boundaries with architects, software and design/verification teams to define and improve the emulation platform - Build flow for emulation models with optimum frequency and emulation footprint - Write emulation test-benches for single and multi chiplet models and transactors, monitors and harness components - Write test plans focusing on unique functional coverage, performance, power extraction and low level software development - Execute test plans, summarize the results and share feedback with project stakeholders - Advanced degree in electrical engineering, computer engineering, or computer science - Proven experience in emulation/design, with a strong track record of successful projects - Proficiency with Synopsys Zebu and/or Cadence Palladium, with the ability to adapt to various emulation platforms as needed - Understanding of logic design and mapping design to emulation hardware - Knowledge in Verilog/system Verilog - Knowledge of emulation tools, flows, scripting and automation - Good problem solving skills, organizational and communication skills - Good English language skills (written and spoken) - Experience with Cadence Palladium - Knowledge of C, C++ or SystemC - Knowledge of RISC-V, CPU microarchitecture, machine learning, die-to-die, memory controllers, PCIe, UCIe - Understanding of verification - Fluency in Japanese - Japanese work visa

Location: Japan

Salary range: None - None

2025-06-17

Chiplet Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for synthesis and place and route using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus. This role isbased out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Synthesis and Place and Route using industry standard tools for high speed CPU core design - Plan out resources, schedule, project PPA - Develop strategies to deliver reproducible design convergence results - Help to create and refine synthesis and PNR flow for the project team - Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure - Develop and recommend better design methodologies to enable better timing convergence - Plan out resources, schedule, project PPA - Guide and mentor junior engineers - PV convergence (including static timing and power analysis) - Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks - Scripting in an interpreted language, minimum TCL in addition to at least one other - Advanced degree in electrical, computer engineering or computer science - Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure - Experience with PV convergence, including static timing and power analysis - Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks - Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools - Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs - Expertise in timing closure and block/chip levels and ECO flows - Experience with scripting in an interpreted language (Python, TCL) - Willingness to work with others in a highly complex decision space - Skills at developing an implementation plan, monitoring key indicators and communicating resource needs, as well as scoping risk to deliver value on schedule - Excellent verbal and written communication in English, and collaboration skills - Fluency in Japanese. - Japanese work visa.

Location: Japan

Salary range: None - None

2025-06-17

Chiplet Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for synthesis and place and route using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus. This role isHybrid, based out of Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Synthesis and Place and Route using industry standard tools for high speed CPU core design. - Perform all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks and design closure. - Develop and recommend better design methodologies to enable better timing convergence. - PV convergence (including static timing and power analysis). - Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. - Scripting in an interpreted language, minimum TCL in addition to at least one other - Bachelor, Master or PhD degree in electrical, computer engineering or computer science. - At least 10 years of relevant industry experience. - Experience with integrated circuit design tools (e.g. Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. - Experience with PV convergence, including static timing and power analysis. - Experience with chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro-mitigation checks. - Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools. - Strong experience in SoC/ASIC/GPU/CPU design flows on taped out designs. - Expertise in timing closure and block/chip levels and ECO flows. - Experience with scripting in an interpreted language (Python, TCL). - Willingness to work with others in a highly complex decision space. - Excellent verbal and written communication in English, and collaboration skills.

Location: United States

Salary range: None - None

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