Tenstorrent's Posts (144)

RTL Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will develop and customize chiplets, including but not limited to chiplet die-to-die interconnect. This role is on-site, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Work on front-end RTL integration of CPU cores, AI cores, interface IPs and high-speed I/Os - Write specifications, micro-architecture, create RTL implementation plan, implement the plan based on the micro-architecture specification - Work closely with verification, emulation and physical design teams to transform RTL to GDSII - Work on post-silicon validation activities - Contribute to design methodologies driving continuous improvement for front-end design - Advanced degree in electrical, computer engineering or computer science - At least 5 years industry experience in logic design - Knowledge of CPU architecture, SoC architecture - Experience with CPU/SoC RTL implementation with Verilog/SystemVerilog - Experience with high-speed I/O controllers & PHY integration, such as PCI-express, DDR, HBM or UCIe… - Proficiency in RTL design and front-end tools and simulators (VCS/IUS), CDC/Lint checkers - Proficiency in physical design tools like synthesis (DC), static timing checks (STA), DFT - Good problem solving skills, organizational and communication skills - Good English language skills (written and spoken)

Location: Japan

Salary range: None - None

Sr. Staff, Digital Design Verification Engineer, Chiplets

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for an experienced Digital DV Engineer to join our team. At Tenstorrent you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated team. We are looking for a DV Engineer to develop verification methodology for our products. This role isremote, based out of Taiwan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Verification of Tenstorrent's digital IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, emulation - Creation of test plans - Writing testbenches, checkers and tests, models, assertions and irritators - Creating functional coverage points - Reviewing verification results and metrics and, driving the verification convergence towards tape-out - Performance and power verification and validation of Tenstorrent's IP and SOC - At least 8 years of experience in hardware verification languages (SystemVerilog, SystemC) - Bachelor/Master in Electrical/Computer Engineering/Engineering Science - Experience with UVM and coverage driven constrained random verification - Experience with Low power verification techniques - Excellent programming skills. C/C++ as well as scripting languages (Perl, tcl) - Deep interest in computer architecture

Location: 泰安, New Taipei City, Taiwan

Salary range: None - None

Staff, Software Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will develop software for our RISC-V CPU chiplet. This role ison-site, based out of Tokyo, Japan. Responsibilities: Experience & Qualifications: Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Design, develop, and optimize system software for RISC-V-based systems. - Collaborate with cross-functional teams to define software requirements and specifications. - Participate in development and maintenance of software stacks, including Operating Systems, drivers, firmware, and libraries, to support our hardware platforms. - Implement and optimize system software, and contribute to workload optimization. - Troubleshoot and resolve software and system-level issues. - Develop and maintain software development processes, tools, and methodologies to ensure high-quality code and timely delivery. - Stay up-to-date and engaged with the latest industry trends and advancements in RISC-V, AI, and ML technologies. - Regular communication/travel to Australia and USA to meet with the team. - Fluent in English - Bachelor's degree or higher in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent work experience. - Strong debugging, problem-solving, and analytical skills. - Excellent communication and teamwork abilities. - Proven experience in delivering complex system software products to customers and internal stakeholders. - 5+ years of professional experience in system software engineering. - Solid understanding of RISC-V architecture and instruction set. - Experience with Linux kernel development and device driver programming. - Experience with product development of embedded software and real-time solutions is a plus. - Strong coding skills in C/C++/ASM and one or more of Python, Rust or Go.

Location: Japan

Salary range: None - None

STA Lead, Physical Design Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for STA timing analysis using industry standard tools for high-speed CPU core design. Knowledge of cutting edge silicon technology 5nm and lower and multi Ghz design is a plus. This role isRemote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Full chip timing analysis from early investigation to final implementation and tape out. - Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure. - Work with architects and logic designers to generate block and full chip timing constraints. - Analyze scenarios and margin strategies with Synthesis & Design team. - Partner with physical design teams to close and sign off the designs through PnR and ECO cycles. - PhD, Masters or Bachelors Degree in EE, EECS or CS. - Hands-on experience in ASIC timing constraints generation and timing closure. - Expertise and advanced knowledge of industry standard timing EDA tools (Prime Time, StarRC etc.). - Deep understanding and experience in timing closure of various functional and test modes - Expertise in deep-sub micron processes (Crosstalk delay, noise glitch, POCV, IR-STA). - Proficient in scripting (TCL, Perl, Python, csh/bash). - Problem solver, Efficient written and verbal communication, Excellent organization skills and Mentorship quality. - Self starter and highly motivated. - Ability to work cross-functionally with various teams and be productive under aggressive schedules.

Location: United States

Salary range: None - None

Verification Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will ensure functionality and performance of the system. This role ishybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Nice to Have: Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency,asylee and refugeeinformation and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Verify Tenstorrent’s digital IP and SoC logic at chiplet integration level, using predominantly an UVM based verification methodology, - Build and improve components of verification infrastructure including model builds and simulation/regression runs, - Create verification components like testbenches, checkers and test generators, - Add assertions and coverages along associated methodologies, - Build verification test plans for subsystems, align them with project stakeholders, implement test suites, summarize the results and share feedback with project stakeholders - Publish and review verification metrics and drive convergence towards tape-out, - Work across boundaries with architects, software and design/emulation teams, - Guide and mentor junior engineers. - Advanced degree in electrical, computer engineering or computer science - Proven experience in CPU or SoC verification - Experience with verification flows, scripting and automation - Good knowledge of logic design - Knowledge of Verilog//v2k/system Verilog - Strong problem solving skills - Excellent organizational and communication skills - Good English language skills (written and spoken) - Knowledge of RISC-V, machine learning, die-to-die, memory controllers, PCIe, UCIe - Knowledge of low level drivers and firmware in C - Fluency in Japanese - Japanese work visa

Location: Japan

Salary range: None - None

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