CPU Architecture- Physical Design Lead
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a highly skilled Senior Physical Design Engineer with expertise in high-speed CPU core design to join our team. This role will be working closely with our Architects to develop the next generation of CPU. This role isremote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Experience & Qualifications: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. - Hands-on experience with synthesis and place and route using industry standard tools for next generation high speed CPU core design. - Perform all aspects of design flow from feasibility analysis, logic synthesis, place and route, FEV, power, timing, quality checks, and design closure. - Develop and recommend better design method practices to enable better synthesis convergence. - Plan out resources, schedule, project PPA - The ideal candidate will exhibit behavioral traits that demonstrate: - Willingness to work with others in a highly complex decision space. - Skills at developing an implementation plan monitoring key indicators and communicating resource needs and scoping risk to deliver value on schedule. - Excellent verbal and written communication and collaboration skills. - Bachelors in Computer Engineering or Electrical Engineering with 10+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering (or higher degree) with 10+ years of relevant work experience - Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure. - PV convergence (including static timing and power analysis). - Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks. - Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools. - Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows. - Scripting in an interpreted language (Python, TCL)
Location: United States
Salary range: None - None